In a random access integrated circuit memory chip, binary digits, or bits, are stored in semiconductor memory cells. Individual bits or words of several bits can be accessed at random by addressing selected memory cells or small groups of cells within the memory. The information stored in the addressed memory cells can then be read out. Where the information is relatively permanently stored in the memory cells, the memory is termed a read-only memory. Where, however, the information stored in the memory can be readily and selectively changed, the device is termed a read/write memory. The term random access is often used in a limited sense to apply to these read/write memories; however, the term is used here in its broader sense. It applies to the addressing mode of the device and thus includes such other devices as read-only memories and programmable read-only memories.
With the trend toward extremely miniaturized circuits having a minimum of interconnections, there has been a concomitant increase in the number of memory cells formed on a single minute chip of semiconductor crystal. Single chip integrated circuit memories having a memory capacity of over 64 kilobits (64 K, that is, 65,536 bits) of information are not uncommon. A major limitation on the increased capacity of memory chips is that, with the increase, the production yield decreases substantially. As the size of the memory chip increases, the number of chips which can be fabricated on each semiconductor wafer decreases, and the likelihood that a chip includes one or more defective memory cells or other circuitry increases.
In an effort to increase the yield of functional memory chips per semiconductor wafer, some manufacturers include extra memory cells on each chip. Then, during initial testing or subsequent periodic testing, defective cells can be detected, and those cells can be replaced with the extra cells. The replacement is by means of special addressing circuitry. Such redundant fabrication used with this fault-tolerant addressing offers substantially increased yield over conventional memory chip designs by bypassing hard errors noted in a memory chip during testing.
Another problem encountered in memory systems of all sizes is that a memory chip may be good when placed in a circuit but later suffer some error in its output. The error may be a temporary, "soft" error caused by radiation or the like, or it may be a permanent, "hard" error resulting from some defect in the memory which arises after testing. The avoidance of errors in the memory output is often of critical importance. For example, where a computer system controls a manufacturing process on a production line the presence of a single bit error in the memory output may result in a shutdown of the entire production line. Such shutdowns are costly and time consuming. Thus, it is desirable that the errors be corrected before the computer relies on the information which contains the errors.
In order to detect or even correct such errors which occur during use of a memory system, redundant bits are often added to a word of information bits. These bits are generated from the word of information bits and stored with them in the memory system. During readout, the encoded word, that is, all of the stored information and redundant bits, is accessed. Decoding circuitry can then detect errors and correct one or more errors depending on the degree of redundancy. For example, with the widely used Hamming code four parity bits can be added to an eight bit data word to provide for single bit error correction or five parity bits can be added to the eight bit data word to provide for single bit error correction and double bit error detection.
Such error correction is used primarily in large, multichip memory systems, and each encoded memory word is generally stored as one bit per memory chip. When those bits are then read out as a word, they can be decoded through an error correction circuit to provide the corrected information bits. With no more than one bit of any encoded word stored on any chip, failure of one memory chip can affect no more than one bit of an encoded memory word and, absent other errors, a correct output can be provided. For example, with the code mentioned above, one bit of each word may be stored in each of twelve memory chips. On read-out, the bits from the same address in the several chips are fed through error correction circuitry to provide an eight bit output.
The use of error correction circuitry in a memory system greatly increases the reliability of the system by correcting soft errors, and hard errors which arise after testing.
An object of the present invention is to provide a single chip, random access integrated circuit memory device with a high yield comparable to that of the fault-tolerant addressing system discussed above which also has greater reliability than has heretofore been possible.